Easing the microchip shortage
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The current microchip shortage has vexed technology and manufacturing companies for over two years. Chip production was severely impacted by COVID-19 as production facilities closed, and experts predict it could be another year or two before production rebounds.
Meanwhile, the demand for increasingly complex chips has accelerated, with smart features incorporated into an ever increasing number of products, including washing machines and refrigerators.
Assistant Professor Inna Partin-Vaisband is working to drastically shorten the design-to-market time for microchip manufacturing by removing a primary bottleneck in the design process with artificial intelligence.
In the past 15 years, fast-growing chip design complexity has exceeded electronic design automation capabilities, opening an exponentially increasing gap between the two. Simulations must be run to ensure these circuits work together, as designed, in a process known as convergence. And if the circuits don’t converge, engineers must go back a few steps to fix the problems manually. This failure to know or be able to predict the output quality results in lower performance chips and lost profit if the chips cannot be ready to release to market on time.
Partin-Vaisband is using a fundamentally new approach for circuit global routing, viewing the problem in a different way to the standard design method—by redefining it as an imaging problem. This is achieved by applying deep neural nets—multi-layer computer programs that rely on training data to learn and improve over time, just as a human brain makes connections between neurons.
Currently, chip design is conducted on a CPU, running through the design steps in a sequential manner, with engineers manually fixing problems as they encounter them. Instead, Partin-Vaisband is developing a deep learning framework to accelerate chip design. Just as deep neural nets have been trained to upscale images to a higher resolution and fill in missing details, Partin-Vaisband intends to improve the chip design process by training the model to evaluate thousands or millions of circuit design solutions at a time—orders of magnitude faster. Steps are parallelized on a modern accelerator, which can evaluate thousands or millions of circuit design solutions at a time.
“This project can shift physical design paradigms toward a learning-driven, predictable process,” she said.